As integrated circuit (IC) fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functions increases, however, so does the complexity of the designs, and potential defects associated therewith. Often to meet deadlines, many designers work on a same design simultaneously. The partial designs will then need to be put together to make a final product. The timing is of the essence in making sure that the many portions of the design are finished relatively simultaneously and free of defects. In addition, it is imperative that strict deadlines are followed, in part, because a later design stage may depend on information regarding a preceding stage before meaningful design may be commenced.
FIG. 1 illustrates an exemplarily flow diagram of a typical design process 100 for ICs in accordance with the prior art. The process can be generally divided into a front end design phase and a back end development phase. During the front end phase, an engineer designs and develops a logical representation of an IC from a set of specifications in form of a schematic (stage 102). At a stage 104, the schematic is then loaded into a computer from which a circuit netlist is generated. The netlist defines the entire IC design including all components and interconnections.
Moreover, the IC information may be developed using hardware description language (HDL) and synthesis. With the aid of circuit simulation tools available on computers, a designer can then simulate the functionality of a given circuit at a stage 106. The circuit simulation process may involve several iterations of design modifications and improvements, until the circuit design is finalized at a stage 108.
The back end development involves several stages during which a final circuit layout (physical description) is developed based on the schematic design of the front end. In a stage 110, various building blocks (or cells), as defined by the finalized circuit schematic, are placed within a predefined floor plan. For ICs designed based on array or standard cell technology, the various building circuit blocks are typically pre-defined and made available in a cell library. For example, during the stage 110, a plurality of cells are selected from one or more cell libraries and the cell interconnects are determined. More particularly, groups of cells may be interconnected to function as a flip-flop, shift registers, and the like. The routing of wires to interconnect the cells and achieve the aforementioned goals is preformed during a routing stage 112, typically referred to as conducting paths, wires or nets. Accordingly, in the stage 112, interconnects between circuit elements are routed throughout the layout. In a stage 114, the accuracy of the layout is verified against the schematic and if no errors or design rule violations are found at a stage 116, the circuit layout information is used for the process of fabrication in a stage 118.
Accordingly, layout tracking and verification and/or defect tracking of discovered problems are important parts of manufacturing an IC. These tasks may be partially automated by using a software application. In many software applications where the important data is recorded and appended to the end of a file constantly, a meaningful reordering and reorganizing of the data in that file can be a cumbersome task. For example, for a layout tracking tool, layout designers may update a layout chart periodically and a layout manager needs to sort out the layout chart information to keep track of scheduling. Furthermore, in a defect tracking tool example, interested parties need to open the defect log file, read the file from the beginning to the end repeatedly, analyze the records, and sort them so as to understand and follow the defect cycle (who opened, when it was assigned, when it was accepted, when it was fixed, when it was closed, etc.).
In both of these examples, opening the log file(s), analyzing the records, and reordering them can be a time-consuming task prone to many errors. A software application may be utilized to perform such tasks by, for example, opening the current log file for read and a temp file for write, getting the data from log file one portion at a time, organizing the data, writing the organized data to the temp file, closing the log file, and writing the temp file over the log file. However, one or more of the following drawbacks still remain: (1) IO: read from the top to the bottom of the log file repeatedly; (2) Performance: opening and closing files; and/or (3) Human Error: analyzing and recording the appropriate data.